Wafer Level Chip Size Packaging (WLCSP) technology is a technology in which a whole wafer is packaged and tested before being diced into individual chips. Such a technology is totally different from the conventional packaging technologies, such as Chip On Board (COB), where a whole wafer is thinned and diced into individual chips and then the chips are wire bonded. The size of a chip after being packaged with the WLCSP technology is almost the same as that of a bare chip. The WLCSP technology satisfies the requirements for the microelectronic products, such as light weight, small size (especially in length and thickness) and low cost. A chip packaged with the WLCSP technology realizes its miniaturization, and the cost of the chip is reduced significantly with the decrease in chip size and the increase in wafer size. The WLCSP technology, as a technology that takes into account the IC design, wafer fabrication, packaging test and substrate fabrication as a combination, is a focus in the packaging field and represents a trend of the packaging technologies.
In the WLCSP technology, the pads arranged in the exterior of a semiconductor chip are generally re-distributed, by a re-distribution process, to form an area array of a number of metal bonding balls which are sometimes referred to as solder bumps. The WLCSP technology, due to its process of packaging and testing a whole wafer prior to the dicing, presents the following advantages: first, compared with the conventional art in which the wafer is diced and classified before being packaged, the processes are significantly optimized by directly entering the wafer into the packaging process; in addition, different from the conventional assembly process, all integrated circuits are packaged at one time, the marking process is performed on the wafer directly, and the packaging and testing are done at one time, therefore, the manufacturing time and cost are reduced significantly.
Shellcase Ltd. Israel developed its advanced WLCSP technology, classified ShellOP, ShellOC, and ShellUT, which provide perfect solutions for the packaging of image sensors. Unlike other packaging methods, the Shellcase process requires no lead frames or wire bonding. Briefly, ShellOP utilizes a glass/silicon/glass sandwich structure to enable image-sensing capabilities and to protect the image sensors from being contaminated by external environment. ShellOC adopts the same sandwich structure, but extra cavities are configured on the first glass by spin coating photosensitive epoxy and then exposing and developing it. The extra cavities accommodate the image sensor and micro-lenses thereon for enhancing image quality. ShellOC is thus the packaging solution of choice for image sensors with micro-lenses. In the ShellUT package, cavities are still kept but a second glass is removed so that the associated package height is reduced.
US patent application No. US2001018236, which is assigned to Shellcase Ltd., discloses a packaging structure and a method for forming the packaging structure that are based on the WLCSP technology. As shown in FIG. 1, the disclosed packaging structure includes a substrate 114, a cavity wall 116 on the substrate 114, pads 112, a chip 102 including a photosensitive element 101, and bumps 110. The cavity wall 116 on the substrate 114 is sealed, via the pads 112, over a first surface of the chip 102 to define a cavity 120. An epoxy layer 104 is formed over the other surface of the chip 102, and the other surface of the epoxy layer 104 is covered by a glass layer 106, along the edge of which an intermediate metal layer 108 is formed. The intermediate metal layer 108 is electrically connected to the pads 112 and the bumps 110.
As shown in FIG. 1, T shaped connection points are formed between the pads 112 and the intermediate metal layer 108. Such shaped connection is not reliable since it is prone to break under extreme situations. In addition, the packaging structures formed with the above packaging methods are still too thick to comply with the miniaturization trend of semiconductor devices.
In addition, in the existing technologies the pads on a chip may extend outside to form extension pads so as to enlarge the area of the pads, thereby enhancing the stability of the bonding. However, this results in a reduction in the available area on the wafer for manufacturing the chips. Accordingly, the manufacturing cost is increased. Therefore, there is a demand in the industry for the improvement of the above described packaging structures.